An integrated circuit (IC) is typically made up of many interconnected devices (e.g., transistors) formed on a silicon substrate. The layout of these devices and the manner in which they are interconnected determines the functionality of the IC. As modern ICs become ever more complex, automated design tools have become an essential part of the IC layout development process.
Automated design tools can be used to perform various operations on an IC layout. For example, an automated tool might be used to make optical proximity correction (OPC) modifications or perform design rule checking (DRC) on an IC layout. An automated tool could even be used to create the actual IC layout from a design netlist.
However, while automated tools enable the accurate creation of IC layouts, the complex interactions of the rules embodied in those tools can result in layout imperfections. In other words, while the results of an automated tool may be electrically correct (and even optically correct), the polygons that make up the actual IC layout might include unintended irregularities. These “layout imperfections” are not necessarily defects in the sense that the IC layout may still be electrically correct. However, these layout imperfections may adversely affect layout printability or device performance. Also, such imperfections can significantly increase data volume for a particular IC layout, thereby undesirably increasing layout processing (e.g., OPC, DRC, etc.) and mask production times.
For example, FIG. 1a shows a simple polygon 100 made up of edges 101-108. Polygon 100 could represent a simple wire or interconnect in an IC layout. A notch 111 in the side of polygon 100 represents a common type of layout imperfection. If notch 111 is small, it may cause no significant electrical or optical problems. However, as shown in FIG. 1b, during a fracturing operation notch 111 causes polygon 100 to be split into primitives 121, 122, and 123, along fracture lines 131 and 132. In contrast, FIG. 1c shows a polygon 140 that is substantially similar to polygon 100, but does not have the same notch-type imperfection. As a result, polygon 100 would fracture into a single primitive. Thus, the small imperfection in polygon 100 (i.e., notch 111 shown in FIG. 1b) results in a three-fold increase in data volume after a fracturing operation.
Unfortunately, due to the complexity of modern IC layouts, detecting and correcting this type of layout imperfection (a technique sometimes referred to as “layout beautification”) can be difficult. A method sometimes used to eliminate notch-type imperfections involves applying an oversizing/undersizing technique to entire polygons using a DRC tool. As indicated in FIG. 1d, each edge of polygon 100 is biased outward (oversized). As this biasing takes place, notch 111 formed by edges 102-104 shrinks and eventually disappears. The remaining edges can then be biased inward (undersized) to create a corrected (un-notched) polygon having the same overall dimensions as the original polygon 100.
However, this technique of oversizing and undersizing provides a very limited solution to the problem of layout imperfections. Because the manipulations are applied to the entire polygon, specific layout imperfections cannot be targeted and unintended (undesirable) modifications can occur. Furthermore, this technique can only work on certain very simple layout imperfections. Layout imperfections that are even marginally more complex cannot be corrected in this manner.
Therefore, due to these difficulties in detection and correction, layout imperfections are often ignored. Consequently, layout data file sizes are unnecessarily large and processing of those data files (e.g., OPC, DRC, etc.) is unnecessarily time-consuming. Furthermore, the excess of layout imperfections in conventional layouts also can cause problems during mask production by increasing the complexity of the mask-writing process (i.e., the creation of the mask pattern on the mask substrate). This not only slows manufacturing throughput, but also increases the chances of errors during mask production. Accordingly, it is desirable to provide a method for efficiently, effectively, and flexibly performing layout beautification.